This invention relates to programmable logic devices that have input/output (I/O) circuitry that can be programmed for either differential or single-ended signaling. More particularly, this invention relates to programmable logic devices wherein the I/O circuitry can be programmed to reduce the effects of parasitic I/O pin capacitance and inductance.
Programmable logic devices (PLDs) are known and commonly include circuits/devices referred to as PLAs (programmable logic arrays), FPGAs (field programmable gate arrays), EPLDs (erasable programmable logic devices), EEPLDs (electrically erasable programmable logic devices), and LCAs (logic cell arrays). Such devices allow a user to electrically program standard, off-the-shelf logic elements to meet a user's specific needs.
Many PLDs have enhanced versatility by employing I/O circuitry that can be programmed to receive either differential or single-ended signals. Differential signals are pairs of signals that propagate in parallel and are received by a respective pair of I/O pins. Each signal is usually a logical complement of the other. That is, when one signal is at a high voltage (e.g., a “logical 1”), the other is at a low voltage (e.g., a “logical 0”), and vice versa.
Such I/O circuitry typically includes an input buffer and an output buffer for single-ended signaling, and a differential input buffer for differential signaling. The three buffers are each coupled to the same I/O pin, with the differential input buffer having a second input coupled to another I/O pin to receive the complementary differential signal. For differential signaling, the input and output buffers are disabled and the differential input buffer is enabled. This allows a pair of differential signals to be respectively received at a pair of I/O pins. For single-ended signaling, the differential input buffer is disabled and either the output buffer is disabled and the input buffer is enabled to receive an individual signal from the I/O pin, or the input buffer is disabled and the output buffer is enabled to drive an individual signal to the I/O pin.
A disadvantage of such programmable I/O circuitry is high input pin impedance during differential signaling. Parasitic capacitance is principally caused by the single-ended input and output buffers, because even though they are disabled during differential signaling, which renders them inoperative, they still form a capacitive load on the I/O pin. Parasitic impedance is mainly caused by wire and other pin connections, and is especially high in the case of wire-bonded packages. High input capacitance or inductance degrades signal quality, which can cause timing and/or logic errors in transmitted data, control, and address signals. Such errors can adversely affect an entire computer system. Moreover, high input impedance is particularly detrimental to speed-sensitive differential signals, which typically operate at high data rates. As process technologies improve and data rates increase, the adverse effects of high input impedance can be expected to increase further.
In view of the foregoing, it would be desirable to be able to provide I/O circuitry that can be programmed for either differential or single-ended signaling without the adverse effects of high parasitic input pin impedance during differential signaling. Further, it would be desirable to be able to provide I/O circuitry that can compensate for parasitic capacitive and inductive loading of I/O pins.